State machines are widely used in hardware designs to maintain control of systems which have predictable states. State machines are typically clocked; that is, a typical state machine operates under control of a clock, sometimes referred to as a state clock, which provides a periodic clock signal to control synchronous operation of the logic in the state machine.
FIG. 1a shows a typical state machine in block diagram form. The state machine receives certain inputs 11 as well as a clock signal 12 and outputs 15 are provided by the state machine 10. As is well known, the state machine processes the inputs (which may include the prior state of the state machine in the prior clock cycle or cycles). These inputs are processed according to the logic designed into the state machine such that certain outputs are predictably provided as a consequence of the inputs and, in some cases, the poor state of the state machine.
FIG. 1b shows a more detailed example of a typical state machine. It includes some form of logic 17 (such as a PLA and/or random gates and/or random logic) as well as an output register 19 and a state register 21. A clock signal 23 is provided to the state register 21 as well as the output register 19 in order to clock signals into and out of the state register and the output register. It will be appreciated that a plurality of output registers as well as a plurality of state registers may be provided, often in a parallel format, in order to provide a multiple bit state or multiple bit output. The clock signal 23 may also be applied to the logic 17 if the logic is synchronous rather than combinatorial; often, logic 17 is purely combinatorial and thus no clock is required for this logic as long as the clock signal is supplied to the output registers 19 and the state register 21 and as long as normal set up and hold times for these registers are followed. Inputs 33 to the logic 17 are processed by the logic 17 along with, as shown in FIG. 1b the prior state of the state machine which is fed back through line 35 from the state register 21. The processing of the inputs and optionally the prior state through line 35 results in a new output appearing on output 29 as well as a new state appearing on line 25 which are both clocked into the respective registers 19 and 21 to provide new outputs at outputs 31 and 27.
The use of state machines in the prior art to control various logic systems is well known. For example, state machines are often used to control inputs/output (I/O) controllers as well as memory controllers, bus controllers and other controllers which interface between logic systems and subsystems.
In prior art systems where a clock is stable, there is typically no problem with respect to maintenance of the state of state machines and state registers. Even with start up irregularities in a clock system (e.g. a system is powered up for the first time resulting in noise and glitches in the clock signal from the start up process), state machines are usually initialized at some initial condition upon start up such that irregularities in the clock signal from the start up process do not effect the state of a state machine upon initialization.
However, there is often a need to remove power from the clock generating circuits in order to reduce power in a logic system during the operation of the system and to resume operation of the system. A typical example is a laptop computer system (sometimes also referred to as a notebook computer or a portable computer) which is operating off of batteries. Other examples include desktop, notebook, portable or laptop computers which include energy conservation systems designed to conserve energy by reducing power consumption even though the source of power is not a battery (e.g. a conventional AC powered computer); these computers (sometimes referred to as "green" computer systems) reduce power to peripherals (e.g. hard disks, display screens, etc.) in order to reduce power consumption and often also reduce power by reducing power to clock signal generators. In this case, it is advantageous to reduce the power provided to the clock generator circuits by, for example, completely removing power or by slowing the clock down (i.e. decreasing the frequency of the clock signal). It will be appreciated that the bussing of clock signals throughout a computer system causes the consumption of a large amount of power. Thus reducing this power (by reducing the power provided to the clock generating circuits) greatly increases battery life and reduces the power consumption of the laptop computer. It is noted that laptop computers may also use conventional AC power from, for example, a wall outlet, and there is a benefit to reducing its power consumption even in this case.
Reducing power to a clock generator during the operation of a system requires that the clock generator be powered up and powered down while the computer (e.g. a laptop or desktop computer) is being used by a user such that the computer maintains values from its interaction with the user. In other words, this reduction of power occurs in the middle of operating the computer, and the user will expect the computer to preserve the state of the computer's operation when it was caused to enter low power mode, such that upon resuming full power or increased power, the user may continue pending operations. For example, a user of a word processing computer program may have typed a letter which is half completed and is being displayed by the computer system. The user may then perform another task which does not require use of the computer system (e.g. photocopying documents), and the computer system recognizes it is idling and causes itself to enter low power mode. When the user returns to the computer, the user will want the computer to exit low power mode and return, as quickly as possible, to the state it was in when it was last used by the user so that the half-typed letter is again displayed on a display screen of the computer system, and the word processing software is again ready to accept data entry (typing, speech recognition, etc.). Thus, the system RAM may continue to receive power during a lower power mode or the data from the RAM may be copied into a non-volatile memory storage device (e.g. a hard disk) prior to entering low-power mode so that upon resuming normal operations when increased power is applied again, the data prior to reducing power will be available to the user again.
It is of course important to also preserve the states of the various state machines and registers in a computer (e.g. laptop or desktop computer) so that upon resuming normal operation that these states are also preserved for continued use upon resuming normal operation. Unfortunately, reducing power to the clock generator circuits (when entering low power mode) and returning power to the clock generation circuits (when, e.g., resuming normal operation) often causes erratic clock signal pulses which violate the input clock requirements for digital logic, particularly logic assembled in an Application Specific Integrated Circuit (ASIC). As a result, state machines which are often implemented in such ASIC logic can be corrupted into incorrect states from such an erratic clock signal generated from powering down a clock generator or from powering up a clock generator in order to resume activity. As noted above, clock signals tend to be erratic during a normal power up sequence, but then the state machines can be reset to a clean "power up" state by an initialization system. However, in transitioning into and out of low power consumption states in a laptop computer, the computer system is still running and the current state needs to be maintained, and thus resetting to a power on state (initialization) is not acceptable as this will usually not be the state of the computer when low power mode was entered.
FIG. 2a shows an example in the prior art of dealing with this problem of erratic clock signals which occur during power up and power down of clock generation circuits during the continued operation of, for example, laptop computers which are entering and exiting low power consumption modes. In particular, FIG. 2a shows an ASIC chip 200 receiving a clock signal at the clock in input 201 and also receiving a "gate in" signal at input 203. The "gate in" signal is used to maintain the state of clocked registers within the ASIC 200 by not providing the clock internally when the "gate in" signal indicates the clock is unstable (due to entry into or exit from low power mode).
The clock input signal which contains the clock signal is applied to an OR gate 205 as one input of that OR gate 205 and the other input of that OR gate is an output 211 from a flip flop 207, which receives as its input the output of another flip flop 209. The flip flop 209 receives as its input the "gate in" signal, and both flip flops 209 and 207 are clocked under control of the clock in input 201 which receives the clock signal.
FIG. 2b shows a waveform diagram of the various signals used in the prior art approach shown in FIG. 2a. The "gate in" signal is generated whenever the laptop computer or other logic system exits or enters a low power consumption mode. That is, this signal indicates that the clock may become unstable as a result of entering or leaving low power consumption mode in a laptop computer or other logic system. During normal operation the "gate in" signal is maintained low such that the clock in input 201 which contains the clock signal 221 shown in FIG. 2b is provided to the circuits in the ASIC chip 200. When the gate in signal 223 becomes high, this indicates that the computer system is entering a low power consumption mode and that the clock generating circuit will receive reduced power (including perhaps no power) and thus may produce erratic clock pulses at any time during which the clock may be unstable during the low power consumption mode. Thus, a predetermined time after signal 223 (the gate in signal) goes high, the gated clock signal 227 appearing at the output of OR gate 205 no longer reflects the clock signal 221; this can be seen at point 231 in FIG. 2b. At a predetermined time (after the gate in signal 223 becomes low, indicating that normal operation will resume) the gated clock signal 227 resumes providing the normal clock input signal appearing at input 201 of the ASIC 200; this is shown at point 233 of FIG. 2b. This method adds delay to the clock signal which can effect its relationship to other clocks in the system resulting in unpredictable operation. Gating the clock has been acceptable in previous systems because bus speeds are moderate and the clock skew from the delay could be tolerated. Now that system and industry bus speeds have increased, the delay cannot be tolerated.
FIG. 2c shows another attempt in the prior art to maintain stable clock signals. In particular, an ASIC 241 is shown as containing a phase lock loop 243 and a clock driver circuit 245 which outputs a clock signal 247 at the output of the driver 245. The output of this driver is also fed back to the phase lock loop in a conventional manner in order for the phase lock loop to lock onto the clock signal and provide a clock signal internal to the ASIC 241 which reflects the input clock signals at input 201 of the ASIC. In this manner, a stable clock locked to the frequency and phase of the input clock is provided internally to the ASIC 241. It will be appreciated, however, that in this situation the clock input to the phase lock loop at input 201 may not be stopped because this input is a reference input to the phase lock loop 243 and stopping the clock will cause the phase lock loop (PLL) to lose its lock onto the input signal. It will also be appreciated that phase lock loops do not instantly lock onto the phase and frequency of input signals and therefore erratic clock signal outputs from the driver 245 of FIG. 2c will result from stopping the clock to the ASIC or from reducing the power to the clock.
FIG. 2d shows a solution following prior art techniques of the embodiment shown in FIG. 2c. Specifically, a gated clock logic 253 is added between the phase lock loop 243 and the clock driver 245 such that the output from the driver 245 is a gated clock as in the embodiment shown in FIG. 2a. The output from the PLL is fed back as an input to the PLL before the clock signal is gated by logic 253; if the feedback signal to the PLL is from the output of the driver 245, then the PLL will start up with erratic clock signals as noted above. It will be appreciated that the gated clock logic 253 shown in FIG. 2d contains logic which is similar to the two flip flops as well as the OR gate shown in FIG. 2a, where an input to the OR gate is from the output of the phase lock loop 243. The embodiment of FIG. 2d has a similar problem to that of the embodiment of FIG. 2a in that the gating of the clock introduces a delay to the clock signal which becomes a problem at higher frequencies due to the clock skew from the delay. Accordingly, it would be advantageous to provide a method and an apparatus for maintaining the state of state machines while an unstable clock is present without also introducing clock delay as a result of the apparatus and method.